Design of a 6.25 Gbps Backplane SerDes with TOP-down Design Methodology

SerDes design exceeding 6.25 Gbps for existing backplanes has to overcome significant signal integrity challenges on channel attenuation, cross talk, and multiple reflections. Adaptive decision feedback equalization becomes a requirement to overcome these challenges. The non-ideality from silicon implementation is not negligible for bit error rate degradation. This paper presents a 6.25 Gbps backplane SerDes design adopting top down design methodology from system level Matlab simulation down to transistor level spice simulation to optimize the architecture and design. The BER performance is predicted with a joint probability density function (PDF) to account for all the impairments at the decision slicer. Song Wu is the architect for TI 6.25 Gbps SerDes. He has worked on signal integrity issues and designed the adaptive decision feedback equalizer for TI since 2000. He joined TI in late 1995 starting with ADSL research program. He holds 11 patents on communication algorithms and chip design. Sridhar Ramaswamy obtained the PhD from the University of Illinois in 1996. He is presently working at Texas Instruments on high-speed receiver design and verification methodologies. He has authored over twenty papers in the areas of design, modeling and simulation and has five patents issued in these fields. Bhavesh Bhakta is a Member of Group Technical Staff at Texas Instruments. He has a decade of high-performance mixed-signal circuit design experience including PLL, CDR, and equalizer designs in deep sub-micron CMOS. Mr. Dallas, where he is currently working on high-speed serial link technology. Robert Payne is a Senior Member of the Technical Staff at Texas Instruments. He is responsible for the design of circuits and systems used in high speed serial backplane equalizers and clock and data recovery circuits. Mr. Payne holds the BEE and MSEE degrees from the Georgia Institute of Technology. 3 Vikas Gupta received his M.S.E.E. (UT-Austin) in 1995. He then joined Texas Instruments as a reliability engineer. Later, he joined the Internet Infrastructure Business Unit working on the analog front-end of high speed SERDES. Currently Vikas is the ESD Platform manager responsible for ESD in CMOS technologies at TI. Bharat Parthasarathy is a Member of the Technical Staff at Texas Instruments. He is responsible for the design of circuits and systems used in high speed clock and data recovery circuits, and verification methodologies. Mr. Parthasarathy holds a MSEE degree from the University of South Florida. Seema Deshpande is the Program Manager in the High Speed Communication and Controls …